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Features
* EE Programmable 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and * * * * * * * *
4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) Available as a 3.3V (10%) Commercial and Industrial Version Simple Interface to SRAM FPGAs Pin Compatible with Xilinx(R) XC17SXXXA and XC17SXXXXL PROMs Compatible with Xilinx Spartan(R)-II, Spartan-IIE and Spartan XL FPGAs in Master Serial Mode Very Low-power CMOS EEPROM Process Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC Packages), 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and 44-lead TQFP Packages for a Specific Density Low-power Standby Mode High-reliability - Endurance: Minimum 10 Write Cycles - Data Retention: 20 Years at 85C
FPGA Configuration Memory AT17N256 AT17N512 AT17N010 AT17N002 AT17N040 3.3V System Support
Description
The AT17N series FPGA Configuration EEPROM (Configurators) provide an easy-touse, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17N series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and 44-lead TQFP, see Table 1. The AT17N series Configurators uses a simple serial-access procedure to configure one or more FPGA devices. The AT17N series configurators can be programmed with industry-standard programmers, Atmel's ATDH2200E Programming Kit or Atmel's ATDH2225 ISP Cable and factory programming. Table 1. AT17N Series Packages
Package 8-lead LAP 8-lead PDIP 8-lead SOIC 20-lead SOIC 44-lead TQFP Note: AT17N256 - Yes Yes Yes - AT17N512/ AT17N010 Yes Yes Use 8-lead LAP Yes -
(1)
AT17N002 Yes - Use 8-lead LAP Yes Yes
(1)
AT17N040 - - - - Yes
1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8lead SOIC package is not available for the AT17N512/010/002 devices, it is possible to use an 8-lead LAP package instead.
Rev. 3020A-CNFG-05/03
1
Pin Configuration
8-lead LAP
DATA CLK RESET/OE CE
1 2 3 4
8 7 6 5
VCC VCC (SER_EN) DC GND
8-lead SOIC
DATA CLK RESET/OE CE
1 2 3 4
8 7 6 5
VCC VCC (SER_EN) DC GND
8-lead PDIP
DATA CLK RESET/OE CE
1 2 3 4
8 7 6 5
VCC VCC (SER_EN) DC GND
20-lead SOIC
DATA NC CLK NC NC NC NC RESET/OE NC CE
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC NC VCC (SER_EN) NC NC NC NC DC NC GND
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AT17N256/512/010/002/040
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AT17N256/512/010/002/040
44 TQFP
NC CLK NC NC DATA NC VCC NC NC VCC (SER_EN) NC 44 43 42 41 40 39 38 37 36 35 34
NC NC NC NC NC NC DC NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11
12 13 14 15 16 17 18 19 20 21 22
33 32 31 30 29 28 27 26 25 24 23
NC NC NC NC NC NC NC NC NC NC DC
NC RESET/OE NC CE NC NC GND NC NC DC NC
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3020A-CNFG-04/10/03
Block Diagram
SER_EN
POWER ON RESET
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration EEPROM without requiring an external intelligent controller. The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven High, the configuration EEPROM resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the AT17N series configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven Low, the counter and the DATA output pin are enabled. When RESET/OE is driven High again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE. Upon power-up, the address counter is automatically reset.
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AT17N256/512/010/002/040
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AT17N256/512/010/002/040
Pin Description
AT17N256 8 DIP/ SOIC 1 2 3 4 5 O O I 6 - 7 8 20 SOIC 1 3 8 10 11 13 - 18 20 AT17N512/ AT17N010 8 DIP/ LAP 1 2 3 4 5 6 - 7 8 20 SOIC 1 3 8 10 11 13 - 18 20 8 LAP 1 2 3 4 5 6 - 7 8 AT17N002 20 SOIC 1 3 8 10 11 13 - 18 20 44 TQFP 40 43 13 15 18 21 23 35 38 AT17N040 44 TQFP 40 43 13 15 18 21 23 35 38
Name DATA CLK RESET/OE CE GND DC DC VCC(SER_EN) VCC
I/O I/O I I I
DATA CLK RESET/OE
Three-state DATA output for configuration. Open-collector bi-directional pin for programming. Clock input. Used to increment the internal address and bit counter for reading and programming. Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data output driver. The logic polarity of this input is programmable as either RESET/OE or RESET/OE. For most applications, RESET should be programmed active Low. This document describes the pin as RESET/OE. Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the Two-Wire Serial Programming mode (SER_EN Low). Ground pin. A 0.2 F decoupling capacitor between VCC and GND is recommended. Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low enables the Two-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC. 3.3V (10%) Commercial and Industrial power supply pin. NC pins are No Connect pins, which are not internally bonded out to the die. DC pins are No Connect pins internally connected to the die. It is not recommended to connect these pins to any external signal.
CE
GND VCC(SER_EN)
VCC NC DC
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3020A-CNFG-04/10/03
FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory. The AT17N Serial Configuration EEPROM has been designed for compatibility with the Master Serial mode. This document discusses the master serial mode configuration of Atmel AT17N series configuration memories, pin compatible with Spartan-II, Spartan-IIE and Spartan XL OTP PROMs.
Control of Configuration
Most connections between the FPGA device and the AT17N Serial EEPROM are simple and self-explanatory. * * * * The DATA output of the AT17N series configurator drives DIN of the FPGA devices. The master FPGA CCLK output drives the CLK input of the AT17N series configurator. SER_EN must be connected to VCC (except during ISP). The CE and OE/Reset are driven by the FPGA to enable output data buffer of the EEPROM.
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the Two-Wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. The AT17N series configurators enter a low-power standby mode whenever CE is asserted High. In this mode, the AT17N256 configurator consumes less than 50 A of current at 3.3V (100 A for the AT17N512/010 and 200 A for the AT17N002/040).
Standby Mode
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AT17N256/512/010/002/040
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AT17N256/512/010/002/040
Absolute Maximum Ratings*
Operating Temperature.................................... -40C to +85C Storage Temperature ..................................... -65 C to +150C Voltage on Any Pin with Respect to Ground ..............................-0.1V to VCC +0.5V Supply Voltage (VCC) .......................................... 3.0V to +3.6V Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
Operating Conditions
3.3V Symbol Description Commercial VCC Industrial Supply voltage relative to GND -0C to +70C Supply voltage relative to GND -40C to +85C Min 3.0 3.0 Max 3.6 3.6 Units V V
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3020A-CNFG-04/10/03
DC Characteristics
VCC = 3.3V 10%
AT17N256 Symbol VIH VIL VOH VOL VOH VOL ICCA IL Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage (IOH = -2.5 mA) Low-level Output Voltage (IOL = +3 mA) High-level Output Voltage (IOH = -2 mA) Low-level Output Voltage (IOL = +3 mA) Supply Current, Active Mode Input or Output Leakage Current (VIN = VCC or GND) Commercial ICCS Supply Current, Standby Mode Industrial -10 Industrial Commercial 2.4 0.4 5 10 50 100 -10 Min 2.0 0 2.4 0.4 2.4 0.4 5 10 100 100 -10 Max VCC 0.8 AT17N512/ AT17N010 Min 2.0 0 2.4 0.4 2.4 0.4 5 10 150 150 Max VCC 0.8 AT17N002/ AT17N040 Min 2.0 0 2.4 0.4 Max VCC 0.8 Units V V V V V V mA A A A
AC Characteristics
VCC = 3.3V 10%
AT17N256 Commercial Symbol TOE(1) TCE(1) TCAC TOH TDF(2) TLC THC TSCE THCE THOE FMAX Notes:
(1)
AT17N512/010/002/040 Commercial Min Max 50 55 55 0 55 50 25 25 30 0 25 10 15 25 25 35 0 25 10 0 50 Industrial Min Max 55 60 60 Units ns ns ns ns ns ns ns ns ns ns MHz
Industrial Min Max 55 60 80 0
Description OE to Data Delay CE to Data Delay CLK to Data Delay Data Hold from CE, OE, or CLK CE or OE to Data Float Delay CLK Low Time CLK High Time CE Setup Time to CLK (to guarantee proper counting) CE Hold Time from CLK (to guarantee proper counting) OE High Time (guarantees counter is reset) Maximum Clock Frequency
Min
Max 50 60 75
0 55 25 25 35 0 25 10
25 25 60 0 25
1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
8
AT17N256/512/010/002/040
3020A-CNFG-04/10/03
AT17N256/512/010/002/040
AC Characteristics
CE TSCE RESET/OE TLC CLK TOE TCE DATA TOH TCAC TOH TDF THC THOE TSCE THCE
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3020A-CNFG-04/10/03
Thermal Resistance Coefficients(1)
Package Type 8CN4 Leadless Array Package (LAP) JC [C/W] JA [C/W](2) 8P3 Plastic Dual Inline Package (PDIP) JC [C/W] JA [C/W](2) JC [C/W] JA [C/W](2) JC [C/W] JA [C/W](2) JC [C/W] JA [C/W](2) - - - - 17 62 AT17N256 - - 37 107 45 150 AT17N512/ AT17N010 45 135.71 37 107 - - AT17N002 45 159.60 - - - - AT17N040 - - - - - - - - 17 62
8S1
Plastic Gull Wing Small Outline (SOIC)
20S2
Plastic Gull Wing Small Outline (SOIC)
44A
Thin Plastic Quad Flat Package (TQFP)
Notes:
1. For more information refer to the "Thermal Characteristics of Atmel's Packages", available on the Atmel web site. 2. Airflow = 0 ft/min.
10
AT17N256/512/010/002/040
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AT17N256/512/010/002/040
Figure 1. Ordering Code
AT17N256-10PC
Voltage 3.3V 10%
+ -
Size (Bits) 256 = 256K 512 = 512K 010 = 1M 002 = 2M 040 = 4M
Package C P N S = 8CN4 = 8P3 = 8S1 = 20S2
Temperature C = Commercial I = Industrial
TQ = 44A
Package Type 8CN4 8P3 8S1 20S2 44A 8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package (LAP) - Pin-compatible with 8-lead SOIC/VOID Packages 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP)
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3020A-CNFG-04/10/03
Ordering Information
Memory Size 256-Kbit Ordering Code AT17N256-10PC AT17N256-10NC AT17N256-10SC AT17N256-10PI AT17N256-10NI AT17N256-10SI 512-Kbit AT17N512-10CC AT17N512-10PC AT17N512-10SC AT17N512-10CI AT17N512-10PI AT17N512-10SI 1-Mbit AT17N010-10CC AT17N010-10PC AT17N010-10SC AT17N010-10CI AT17N010-10PI AT17N010-10SI 2-Mbit AT17N002-10CC AT17N002-10SC AT17N002-10TQC AT17N002-10CI AT17N002-10SI AT17N002-10TQI 4-Mbit AT17N040-10TQC AT17N040-10TQI Package 8P3 8S1 20S2 8P3 8S1 20S2 8CN4 8P3 20S2 8CN4 8P3 20S2 8CN4 8P3 20S2 8CN4 8P3 20S2 8CN4 20S2 44A 8CN4 20S2 44A 44A 44A Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C)
12
AT17N256/512/010/002/040
3020A-CNFG-04/10/03
AT17N256/512/010/002/040
Packaging Information
8CN4 - LAP
Marked Pin1 Indentifier
E
D
A A1
Top View
0.10 mm TYP
Side View
L1
Pin1 Corner
8
1
e
7 2
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.94 0.30 0.45 5.89 4.89 NOM 1.04 0.34 0.50 5.99 5.99 1.27 BSC 1.10 REF 0.95 1.25 1.00 1.30 1.05 1.35 1 1 MAX 1.14 0.38 0.55 6.09 6.09 1 NOTE
6
3
A
b
5 4
A1 b D E
e1
L
e e1 L L1
Bottom View
Note: 1. Metal Pad Dimensions.
11/14/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm, Leadless Array Package (LAP) DRAWING NO. 8CN4 REV. A
R
13
3020A-CNFG-04/10/03
8P3 - PDIP
E E1
1
N
Top View
c eA
End View
D e D1 A2 A
SYMBOL
COMMON DIMENSIONS (Unit of Measure = inches) MIN NOM MAX NOTE
A A2 b b2 b3 c D 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 BSC 0.300 BSC 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365
0.210 0.195 0.022 0.070 0.045 0.014 0.400
2
5 6 6
3 3
b2 b3
4 PLCS
L
D1 E E1 e eA L
b
0.325 0.280
4 3
Side View
4 0.150 2
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B
R
14
AT17N256/512/010/002/040
3020A-CNFG-04/10/03
AT17N256/512/010/002/040
8S1 - SOIC
3
2
1
H
N
Top View
e B A
D
Side View
SYMBOL A
COMMON DIMENSIONS (Unit of Measure = mm) MIN - - - - - NOM - - - - - 1.27 BSC - - - - 6.20 1.27 MAX 1.75 0.51 0.25 5.00 4.00 NOTE
A2
C
B C D E
L E
e H L
End View
Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
10/10/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. A
R
15
3020A-CNFG-04/10/03
20S2 - SOIC
C
1
EH
N
Top View
A1
End View
COMMON DIMENSIONS (Unit of Measure = inches)
e
b A D
SYMBOL
MIN
L
NOM
MAX
NOTE
A A1 b C D
0.0926 0.0040 0.0130 0.0091 0.4961 0.2914 0.3940 0.0160 0.050 BSC
0.1043 0.0118 0.0200 0.0125 0.5118 0.2992 0.4190 0.050 3 1 2 4
Side View
E H L e
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information. 2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006") per side. 3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. "L" is the length of the terminal for soldering to a substrate. 5. The lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm 1/9/02 (0.024") per side.
R
2325 Orchard Parkway San Jose, CA 95131
TITLE 20S2, 20-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)
DRAWING NO. 20S2
REV. A
16
AT17N256/512/010/002/040
3020A-CNFG-04/10/03
AT17N256/512/010/002/040
44A - TQFP
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 11.75 9.90 11.75 9.90 0.30 0.09 0.45 NOM - - 1.00 12.00 10.00 12.00 10.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 12.25 10.10 12.25 10.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 44A REV. B
R
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3020A-CNFG-04/10/03
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Available on web site
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3020A-CNFG-04/10/03 xM

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